The invention relates to fabrication of electronic component assemblies, and in particular to a method of soldering components together.
Fabrication of circuit assemblies typically involves some soldering of components. For example, the interconnection pads of silicon integrated circuit chips can be soldered directly to interconnection substrates or may be mounted in chip carriers which in turn are soldered to the substrates. Recently, it has also been proposed that chips could be soldered to a silicon wafer to provide a new type of wafer scale integration assembly for very large scale integrated circuits. (See, for example, U.S. patent application of Herrero and Schaper, Ser. No. 658,799, filed Oct. 9, 1984 and assigned to the present assignee.)
In the usual case of soldered components to supporting substrates, it is desirable to achieve a large stand-off height (the gap between a component and a supporting substrate) to permit inclusion of conductors or other elements under the component to provide improved reliability and/or easy cleaning. The need for large stand-off heights requires large solder mounds formed between the component and substrate, which mounds must also have a fairly uniform height distribution. For example, a wafer scale integration application could require a maximum deviation of only .+-.5 .mu.m in solder height for 30 .mu.m height solder bumps.
Various methods are available for producing large solder mounds on the component, the most common techniques being vapor deposition and electroplating. Such techniques can routinely achieve bump heights of 125 .mu.ms. While adequate, such techniques require fairly long processing times and special equipment which could adversely affect the economies of fabricating the assemblies.
It is, therefore, an object of the invention to provide a method of depositing solder mounds to electronic components in an economical fashion.